Abstract: This work deals with the designing of an efficient low noise amplifier for 10.00 GHz applications. The amplifier is designed using Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) ATF – 36077 with inductive source degeneration technique which is one of the techniques to improve the stability of the potentially unstable device and make it unconditionally stable. Also, different substrates are used for designing the LNA to identify the suitable substrate that gives optimum results. It is observed that the noise immunity is more in Low Noise Amplifier (LNA) designed using RT Duroid 5880 substrate. This design resulted in noise figure of 0.859 dB and power gain of 15.530 dB. The comparative analysis of the LNA design is discussed in this paper.
Abstract: It is necessary to realize new biomedical wireless communication systems which send the signals collected from various bio sensors located at human body in order to monitor our health. Also, it should seamlessly connect to the existing wireless communication systems. A 5.8 GHz ISM band low power RF front-end receiver for a biomedical wireless communication system is implemented using a 0.5 µm SiGe BiCMOS process. To achieve low power RF front-end, the current optimization technique for selecting device size is utilized. The implemented low noise amplifier (LNA) shows a power gain of 9.8 dB, a noise figure (NF) of below 1.75 dB, and an IIP3 of higher than 7.5 dBm while current consumption is only 6 mA at supply voltage of 2.5 V. Also, the performance of a down-conversion mixer is measured as a conversion gain of 11 dB and SSB NF of 10 dB.
Abstract: We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for a three dimensional ultrasound bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface a 2-D array of high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together. Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm2 and the full chip occupies a total silicon area of 10x6.8 mm².
Abstract: In this work we present a solution for DAGC (Digital
Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4
GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used
enables gain control over Low Noise Amplifier (LNA) and a
Variable Gain Amplifier (VGA). The control over those signals is
performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better
signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the
average power of the baseband signal close to the desired set point.
DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and
actual gain setting, adjusting a gain factor of the accumulation, and
applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying
the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the
DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.
Abstract: This paper presents a novel approach for the design of
microwave circuits using Adaptive Network Fuzzy Inference
Optimizer (ANFIO). The method takes advantage of direct synthesis
of subsections of the amplifier using very fast and accurate ANFIO
models based on exact simulations using ADS. A mapping from
course space to fine space known as space mapping is also used. The
proposed synthesis approach takes into account the noise and
scattering parameters due to parasitic elements to achieve optimal
results. The overall ANFIO system is capable of designing different
LNAs at different noise and scattering criteria. This approach offers
significantly reduced time in the design of microwave amplifiers
within the validity range of the ANFIO system. The method has been
proven to work efficiently for a 2.4GHz LNA example. The S21 of
10.1 dB and noise figure (NF) of 2.7 dB achieved for ANFIO while
S21 of 9.05 dB and NF of 2.6 dB achieved for ANN.
Abstract: A 1.2 V, 0.61 mA bias current, low noise amplifier
(LNA) suitable for low-power applications in the 2.4 GHz band is
presented. Circuit has been implemented, laid out and simulated using
a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB
power gain a noise figure NF< 2.28 dB and a 1-dB compression point
of -15.69 dBm, while dissipating 0.74 mW. Such performance make
this design suitable for wireless sensor networks applications such as
ZigBee.
Abstract: A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.
Abstract: In first stage of each microwave receiver there is Low
Noise Amplifier (LNA) circuit, and this stage has important rule in
quality factor of the receiver. The design of a LNA in Radio
Frequency (RF) circuit requires the trade-off many importance
characteristics such as gain, Noise Figure (NF), stability, power
consumption and complexity. This situation Forces desingners to
make choices in the desing of RF circuits. In this paper the aim is to
design and simulate a single stage LNA circuit with high gain and
low noise using MESFET for frequency range of 5 GHz to 6 GHz.
The desing simulation process is down using Advance Design
System (ADS). A single stage LNA has successfully designed with
15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3
GHz. Also the designed LNA should be working stably In a
frequency range of 5 GHz to 6 GHz.