Abstract: Hall sensor is widely used to measure rotation angle. When the Hall voltage is measured for linear displacement, it is converted to angular displacement using arctangent function, which requires a large lookup table. In this paper, a lookup table reduction technique is presented for angle measurement. When the input of the lookup table is small within a certain threshold, the change of the outputs with respect to the change of the inputs is relatively small. Thus, several inputs can share same output, which significantly reduce the lookup table size. Its error analysis was also performed, and the threshold was determined so as to maintain the error less than 1°. When the Hall voltage has 11-bit resolution, the lookup table size is reduced from 1,024 samples to 279 samples.
Abstract: Deformable part models achieve high precision in
pedestrian recognition, but all publicly available implementations are
too slow for real-time applications. We implemented a deformable
part model algorithm fast enough for real-time use by exploiting
information about the camera position and orientation. This
implementation is both faster and more precise than alternative
DPM implementations. These results are obtained by computing
convolutions in the frequency domain and using lookup tables to
speed up feature computation. This approach is almost an order of
magnitude faster than the reference DPM implementation, with no
loss in precision. Knowing the position of the camera with respect to
horizon it is also possible prune many hypotheses based on their
size and location. The range of acceptable sizes and positions is
set by looking at the statistical distribution of bounding boxes in
labelled images. With this approach it is not needed to compute the
entire feature pyramid: for example higher resolution features are
only needed near the horizon. This results in an increase in mean
average precision of 5% and an increase in speed by a factor of
two. Furthermore, to reduce misdetections involving small pedestrians
near the horizon, input images are supersampled near the horizon.
Supersampling the image at 1.5 times the original scale, results in
an increase in precision of about 4%. The implementation was tested
against the public KITTI dataset, obtaining an 8% improvement in
mean average precision over the best performing DPM-based method.
By allowing for a small loss in precision computational time can be
easily brought down to our target of 100ms per image, reaching a
solution that is faster and still more precise than all publicly available
DPM implementations.
Abstract: The coefficient diagram method is primarily an algebraic control design method whose objective is to easily obtain
a good controller with minimum user effort. As a matter of fact, if a
system model, in the form of linear differential equations, is known,
the user only need to define a time-constant and the controller order.
The later can be established regarding the expected disturbance type
via a lookup table first published by Koksal and Hamamci in 2004.
However an inaccuracy in this table was detected and pointed-out in
the present work. Moreover the above mentioned table was expanded
in order to enclose any k order type disturbance.
Abstract: .Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions using FPGA. Implementation method with resource/speed tradeoff is proposed to handle signed decimal numbers. The VHDL coding developed is tested using Xilinx XC V50hq240 Chip. To improve the speed of operation a lookup table method is used. The problems involved in using a lookup table (LUT) for a nonlinear function is discussed. The percentage saving in resource and the improvement in speed with an LUT for a neuron is reported. An attempt is also made to derive a generalized formula for a multi-input neuron that facilitates to estimate approximately the total resource requirement and speed achievable for a given multilayer neural network. This facilitates the designer to choose the FPGA capacity for a given application. Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented
Abstract: Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.
Abstract: Custom power is a technology driven product and
service solution which embraces a family devices such as Dynamic
Voltage Restorer (DVR), Distributed Shunt Compensator
(DSTATCOM), Solid State Breaker (SSB) etc which will provide
power quality functions at distribution voltages. The rapid response
of these devices enables them to operate in real time, providing
continuous and dynamic control of the supply including voltage and
reactive power regulation, harmonic reduction and elimination of
voltage dips. This paper presents the benefits of multilevel inverters
when they are used for DPC based custom power devices. Power
flow control mechanism, salient features, advantages and
disadvantages of direct power control (DPC) using lookup table,
SVM, predictive voltage vector and hybrid DPC strategies are
discussed in this paper. Simulation results of three level inverter
based STATCOM, harmonic analysis of multi level inverters are
presented at the end.