Abstract: We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for a three dimensional ultrasound bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface a 2-D array of high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together. Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm2 and the full chip occupies a total silicon area of 10x6.8 mm².
Abstract: This paper presents the design and implementation of a fully integrated Capacitance-to-Voltage Converter (CVC) as the analog front-end for magnetometer interface IC. The application demands very low power solution operating in the frequency of around 20 KHz. The design adapts low power architecture to create low noise electronic interface for Capacitive Micro-machined Lorentz force magnetometer sensor. Using a 0.18-μm CMOS process, simulation results of this interface IC show that the proposed CVC can provide 33 dB closed loop gain, 20 nV/√Hz input referred noise at 20 KHz, while consuming 65 μA current from 1.8-V supply.
Abstract: This paper describes a low-voltage and low-power
channel selection analog front end with continuous-time low pass
filters and highly linear programmable gain amplifier (PGA). The
filters were realized as balanced Gm-C biquadratic filters to achieve a
low current consumption. High linearity and a constant wide
bandwidth are achieved by using a new transconductance (Gm) cell.
The PGA has a voltage gain varying from 0 to 65dB, while
maintaining a constant bandwidth. A filter tuning circuit that requires
an accurate time base but no external components is presented.
With a 1-Vrms differential input and output, the filter achieves
-85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA
were implemented in a 0.18um 1P6M n-well CMOS process. They
consume 3.2mW from a 1.8V power supply and occupy an area of
0.19mm2.