Abstract: This paper deals with the random access procedure in next-generation networks and presents the solution to reduce total service time (TST) which is one of the most important performance metrics in current and future internet of things (IoT) based networks. The proposed solution focuses on the calculation of optimal transmission probability which maximizes the success probability and reduces TST. It uses the information of several idle preambles in every time slot, and based on it, it estimates the number of backlogged IoT devices using Naïve Bayes estimation which is a type of supervised learning in the machine learning domain. The estimation of backlogged devices is necessary since optimal transmission probability depends on it and the eNodeB does not have information about it. The simulations are carried out in MATLAB which verify that the proposed solution gives excellent performance.
Abstract: It is well known that the history between South Korea and Japan influences their international relations; thus, also encompassing their economic relations. In this sense, it is impossible to analyze the latter without understanding the development of the former, which is known for episodes of hostility, like on Japanese colonization, but also had moments of cultural and trade interexchange. Indeed, since 1965, with the establishment of diplomatic relations between both countries, their trade relations have improved, especially after both nations have signed the General Agreement on Tariffs and Trade (GATT). Thereafter, with the establishment of the World Trade Organization (WTO) in 1995, another chapter of their diplomatic and economic relations have been inaugurated. Hence, bearing in mind this history between both nations, this research intends to examine their relations through the analysis of the WTO panels they have engaged in between each other, which are, in chronological order, “DS323: Japan – Import Quotas on Dried Laver and Seasoned Laver”, “DS336: Japan - Countervailing Duties on Dynamic Random Access Memories from Korea”, “DS495: Korea - Import Band, and Testing and Certification Requirements for Radionuclides”, “DS553: Korea - Sunset Review of Anti-Dumping Duties on Stainless Steel Bars” and “DS571: Korea - Measures Affecting Trade in Commercial Vessels”. The objective of this case analysis is to point out what are the areas that are more conflictual between Japan and South Korea in regard to their economic relations so that it is possible to assert on their future (economic) relations and other possible outcomes. And in order to do so, bibliographic and documental research will be made, particularly those involving the WTO and the nations under consideration. Regarding the methods used, it is important to highlight that this is applied research in the field of international economic relations and international law, which follows a hypothetic-deductive model.
Abstract: The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.
Abstract: In this study, the RRAM devices with the TiN/Ti/HfOx/TiN structure were fabricated, then the electrical characteristics of the devices without annealing and after 400 °C and 500 °C of the furnace annealing (FA) temperature processes were compared. The RRAM devices after the FA’s 400 °C showed the lower forming, set and reset voltages than the other devices without annealing. However, the RRAM devices after the FA’s 500 °C did not show any electrical characteristics because the TiN/Ti/HfOx/TiN device was oxidized, as shown in the XPS analysis. From these results, the RRAM devices after the FA’s 400 °C showed the best electrical characteristics.
Abstract: In this work, we demonstrated vertical RRAM device fabricated at the sidewall of contact hole structures for possible future 3-D stacking integrations. The fabricated devices exhibit polarity dependent bipolar resistive switching with small operation voltage of less than 1V for both set and reset process. A good retention of memory window ~50 times is maintained after 1000s voltage bias.
Abstract: HfOx based Resistive Random Access Memory (RRAM) is one of the most widely studied material stack due to its promising performances as an emerging memory technology. In this work, we systematically investigated the effect of metal capping layer by preparing sample devices with varying thickness of Ti cap and comparing their operating parameters with the help of an Agilent-B1500A analyzer.
Abstract: Resistive Random Access Memory (RRAM) had received great amount of attention from various research efforts in recent years, owing to its promising performance as a next generation memory device. In this paper, samples based on TiN/HfOx/Pt stack were prepared and its electrical switching behaviors were characterized and discussed in brief.
Abstract: The application of the synchronous dynamic random
access memory (SDRAM) has gone beyond the scope of personal
computers for quite a long time. It comes into hand whenever a big
amount of low price and still high speed memory is needed. Most of
the newly developed stand alone embedded devices in the field of
image, video and sound processing take more and more use of it. The
big amount of low price memory has its trade off – the speed. In
order to take use of the full potential of the memory, an efficient
controller is needed. Efficient stands for maximum random accesses
to the memory both for reading and writing and less area after
implementation. This paper proposes a target device independent
DDR SDRAM pipelined controller and provides performance
comparison with available solutions.
Abstract: Random Access Memory (RAM) is an important
device in computer system. It can represent the snapshot on how the
computer has been used by the user. With the growth of its
importance, the computer memory has been an issue that has been
discussed in digital forensics. A number of tools have been developed
to retrieve the information from the memory. However, most of the
tools have their limitation in the ability of retrieving the important
information from the computer memory. Hence, this paper is aimed
to discuss the limitation and the setback for two main techniques such
as process signature search and process enumeration. Then, a new
hybrid approach will be presented to minimize the setback in both
individual techniques. This new approach combines both techniques
with the purpose to retrieve the information from the process block
and other objects in the computer memory. Nevertheless, the basic
theory in address translation for x86 platforms will be demonstrated
in this paper.
Abstract: An embedded system for SEU(single event upset) test
needs to be designed to prevent system failure by high-energy particles
during measuring SEU. SEU is a phenomenon in which the data is changed temporary in semiconductor device caused by high-energy particles. In this paper, we present an embedded system for
SRAM(static random access memory) SEU test. SRAMs are on the DUT(device under test) and it is separated from control board which
manages the DUT and measures the occurrence of SEU. It needs to
have considerations for preventing system failure while managing the
DUT and making an accurate measurement of SEUs. We measure the occurrence of SEUs from five different SRAMs at three different
cyclotron beam energies 30, 35, and 40MeV. The number of SEUs of SRAMs ranges from 3.75 to 261.00 in average.
Abstract: Ovshinsky initiated scientific research in the field of
amorphous and disordered materials that continues to this day. The
Ovshinsky Effect where the resistance of thin GST films is
significantly reduced upon the application of low voltage is of
fundamental importance in phase-change - random access memory
(PC-RAM) devices.GST stands for GdSbTe chalcogenide type
glasses.However, the Ovshinsky Effect is not without controversy.
Ovshinsky thought the resistance of GST films is reduced by the
redistribution of charge carriers; whereas, others at that time including
many PC-RAM researchers today argue that the GST resistance
changes because the GST amorphous state is transformed to the
crystalline state by melting, the heat supplied by external heaters. In
this controversy, quantum mechanics (QM) asserts the heat capacity of
GST films vanishes, and therefore melting cannot occur as the heat
supplied cannot be conserved by an increase in GST film
temperature.By precluding melting, QM re-opens the controversy
between the melting and charge carrier mechanisms. Supporting
analysis is presented to show that instead of increasing GST film
temperature, conservation proceeds by the QED induced creation of
photons within the GST film, the QED photons confined by TIR. QED
stands for quantum electrodynamics and TIR for total internal
reflection. The TIR confinement of QED photons is enhanced by the
fact the absorbedheat energy absorbed in the GST film is concentrated
in the TIR mode because of their high surface to volume ratio. The
QED photons having Planck energy beyond the ultraviolet produce
excitons by the photoelectric effect, the electrons and holes of which
reduce the GST film resistance.
Abstract: In this paper optical code-division multiple-access (OCDMA) packet network is considered, which offers inherent security in the access networks. Two types of random access protocols are proposed for packet transmission. In protocol 1, all distinct codes and in protocol 2, distinct codes as well as shifted versions of all these codes are used. O-CDMA network performance using optical orthogonal codes (OOCs) 1-D and two-dimensional (2-D) wavelength/time single-pulse-per-row (W/T SPR) codes are analyzed. The main advantage of using 2-D codes instead of onedimensional (1-D) codes is to reduce the errors due to multiple access interference among different users. In this paper, correlation receiver is considered in the analysis. Using analytical model, we compute and compare packet-success probability for 1-D and 2-D codes in an O-CDMA network and the analysis shows improved performance with 2-D codes as compared to 1-D codes.
Abstract: The most widely used semiconductor memory types
are the Dynamic Random Access Memory (DRAM) and Static
Random Access memory (SRAM). Competition among memory
manufacturers drives the need to decrease power consumption and
reduce the probability of read failure. A technology that is relatively
new and has not been explored is the FinFET technology. In this
paper, a single cell Schmitt Trigger Based Static RAM using FinFET
technology is proposed and analyzed. The accuracy of the result is
validated by means of HSPICE simulations with 32nm FinFET
technology and the results are then compared with 6T SRAM using
the same technology.
Abstract: With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.
Abstract: In this paper, we have presented the effect of varying
time-delays on performance and stability in the single-channel multirate
sampled-data system in hard real-time (RT-Linux) environment.
The sampling task require response time that might exceed the
capacity of RT-Linux. So a straight implementation with RT-Linux is
not feasible, because of the latency of the systems and hence,
sampling period should be less to handle this task. The best sampling
rate is chosen for the sampled-data system, which is the slowest rate
meets all performance requirements. RT-Linux is consistent with its
specifications and the resolution of the real-time is considered 0.01
seconds to achieve an efficient result. The test results of our
laboratory experiment shows that the multi-rate control technique in
hard real-time operating system (RTOS) can improve the stability
problem caused by the random access delays and asynchronization.
Abstract: High performance Resistive Random Access Memory
(RRAM) based on HfOx has been prepared and its temperature
instability has been investigated in this work. With increasing
temperature, it is found that: leakage current at high resistance state
increases, which can be explained by the higher density of traps
inside dielectrics (related to trap-assistant tunneling), leading to a
smaller On/Off ratio; set and reset voltages decrease, which may be
attributed to the higher oxygen ion mobility, in addition to the
reduced potential barrier to create / recover oxygen ions (or oxygen
vacancies); temperature impact on the RRAM retention degradation
is more serious than electrical bias.