Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.
Abstract: This paper presents experimental results on testing the symbol-error-rate (SER) performance of quadrature amplitude modulation (QAM) systems employing symmetric pulse-shaping square-root (SR) filters designed by minimizing the roughness function and by minimizing the peak-to-average power ratio (PAR). The device used in the experiments is the 'bladeRF' software-defined-radio platform. PAR is a well-known measurement, whereas the roughness function is a concept for measuring the jitter-induced interference. The experimental results show that the system employing minimum-roughness pulse-shaping SR filters outperforms the system employing minimum-PAR pulse-shaping SR filters in the sense of SER performance.
Abstract: Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Abstract: In many communication and signal processing
systems, it is highly desirable to implement an efficient narrow-band
filter that decimate or interpolate the incoming signals. This paper
presents hardware efficient compensated CIC filter over a narrow
band frequency that increases the speed of down sampling by using
multiplierless decimation filters with polyphase FIR filter structure.
The proposed work analyzed the performance of compensated CIC
filter on the bases of the improvement of frequency response with
reduced hardware complexity in terms of no. of adders and
multipliers and produces the filtered results without any alterations.
CIC compensator filter demonstrated that by using compensation
with CIC filter improve the frequency response in passed of interest
26.57% with the reduction in hardware complexity 12.25%
multiplications per input sample (MPIS) and 23.4% additions per
input sample (APIS) w.r.t. FIR filter respectively.
Abstract: Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.
Abstract: In this communication, we have made an attempt to design multiplier-less low-pass finite impulse response (FIR) filter with the aid of various mutation strategies of Differential Evolution (DE) algorithm. Impulse response coefficient of the designed FIR filter has been represented as sums or differences of powers of two. Performance of the proposed filter has been evaluated in terms of its frequency response and associated hardware cost. Supremacy of our approach has been substantiated by comparing our result with many of the existing multiplier-less filter design algorithms of recent interest. It has also been demonstrated that DE-optimized filter outperforms Genetic Algorithm (GA) based design by a large margin. Hardware efficiency of our algorithm has further been validated by implementing those filters on a Field Programmable Gate Array (FPGA) chip.
Abstract: Recent experimental evidences have shown that because
of a fast convergence and a nice accuracy, neural networks training
via extended kalman filter (EKF) method is widely applied. However,
as to an uncertainty of the system dynamics or modeling error, the
performance of the method is unreliable. In order to overcome this
problem in this paper, a new finite impulse response (FIR) filter based
learning algorithm is proposed to train radial basis function neural
networks (RBFN) for nonlinear function approximation. Compared
to the EKF training method, the proposed FIR filter training method
is more robust to those environmental conditions. Furthermore , the
number of centers will be considered since it affects the performance
of approximation.
Abstract: Exchange algorithm with constraints on magnitude and phase error separately in new way is presented in this paper. An important feature of the algorithms presented in this paper is that they allow for design constraints which often arise in practical filter design problems. Meeting required minimum stopband attenuation or a maximum deviation from the desired magnitude and phase responses in the passbands are common design constraints that can be handled by the methods proposed here. This new algorithm may have important advantages over existing technique, with respect to the speed and stability of convergence, memory requirement and low ripples.
Abstract: In this paper, an optimal design of linear phase digital
high pass finite impulse response (FIR) filter using Particle Swarm
Optimization with Constriction Factor and Inertia Weight Approach
(PSO-CFIWA) has been presented. In the design process, the filter
length, pass band and stop band frequencies, feasible pass band and
stop band ripple sizes are specified. FIR filter design is a multi-modal
optimization problem. The conventional gradient based optimization
techniques are not efficient for digital filter design. Given the filter
specifications to be realized, the PSO-CFIWA algorithm generates a
set of optimal filter coefficients and tries to meet the ideal frequency
response characteristic. In this paper, for the given problem, the
designs of the optimal FIR high pass filters of different orders have
been performed. The simulation results have been compared to those
obtained by the well accepted algorithms such as Parks and
McClellan algorithm (PM), genetic algorithm (GA). The results
justify that the proposed optimal filter design approach using PSOCFIWA
outperforms PM and GA, not only in the accuracy of the
designed filter but also in the convergence speed and solution
quality.
Abstract: Rounding of coefficients is a common practice in
hardware implementation of digital filters. Where some coefficients
are very close to zero or one, as assumed in this paper, this rounding
action also leads to some computation reduction. Furthermore, if the
discarded coefficient is of high order, a reduced order filter is
obtained, otherwise the order does not change but computation is
reduced. In this paper, the Least Squares approximation to rounded
(or discarded) coefficient FIR filter is investigated. The result also
succinctly extended to general type of FIR filters.
Abstract: In this paper, we demonstrate the adaptive
least-mean-square (LMS) filter modeling using SystemC. SystemC is
a modeling language that allows designer to model both hardware and
software component and makes it possible to design from high level
system of abstraction to low level system of abstraction. We produced
five adaptive least-mean-square filter models that are classed as five
abstraction levels using SystemC proceeding from the abstract model
to the more concrete model.
Abstract: The LMS adaptive filter has several parameters which can affect their performance. From among these parameters, most papers handle the step size parameter for controlling the performance. In this paper, we approach three parameters: step-size, filter tap-size and filter form. The regression analysis is used for defining the relation between parameters and performance of LMS adaptive filter with using the system level simulation results. The results present that all parameters have performance trends in each own particular form, which can be estimated from equations drawn by regression analysis.
Abstract: This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.
Abstract: Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied. In this paper, we propose a design method of variable FIR digital filters with an approximate linear phase characteristic in the passband. The proposed variable FIR filters have some large attenuation in stopband and their large attenuation can be varied by spectrum parameters. In the proposed design method, a quasi-equiripple characteristic can be obtained by using an iterative weighted least square method. The usefulness of the proposed design method is verified through some examples.
Abstract: This paper proposes a new design of spatial FIR
filter to automatically detect water level from a video signal of
various river surroundings. A new approach in this report applies
"addition" of frames and a "horizontal" edge detector to distinguish
water region and land region. Variance of each line of a filtered
video frame is used as a feature value. The water level is recognized
as a boundary line between the land region and the water region.
Edge detection filter essentially demarcates between two distinctly
different regions. However, the conventional filters are not
automatically adaptive to detect water level in various lighting
conditions of river scenery. An optimized filter is purposed so that
the system becomes robust to changes of lighting condition. More
reliability of the proposed system with the optimized filter is
confirmed by accuracy of water level detection.
Abstract: In this paper, we proposed the direct method for converting
Finite-Impulse Response (FIR) filter with low nonzero tap
into Infinite-Impulse Response (IIR) filter using the pre-determined
table. The prony method is used by ghost cancellator which is IIR
approximation to FIR filter which is better performance than IIR and
have much larger calculation difference. The direct method for many
ghost combination with low nonzero tap of NTSC(National Television
System Committee) TV signal in Korea is described. The proposed
method is illustrated with an example.
Abstract: This paper presents an optimal design of linear phase
digital high pass finite impulse response (FIR) filter using Improved
Particle Swarm Optimization (IPSO). In the design process, the filter
length, pass band and stop band frequencies, feasible pass band and
stop band ripple sizes are specified. FIR filter design is a multi-modal
optimization problem. An iterative method is introduced to find the
optimal solution of FIR filter design problem. Evolutionary
algorithms like real code genetic algorithm (RGA), particle swarm
optimization (PSO), improved particle swarm optimization (IPSO)
have been used in this work for the design of linear phase high pass
FIR filter. IPSO is an improved PSO that proposes a new definition
for the velocity vector and swarm updating and hence the solution
quality is improved. A comparison of simulation results reveals the
optimization efficacy of the algorithm over the prevailing
optimization techniques for the solution of the multimodal, nondifferentiable,
highly non-linear, and constrained FIR filter design
problems.
Abstract: In this paper, the least-squares design of variable fractional-delay (VFD) finite impulse response (FIR) digital differentiators is proposed. The used transfer function is formulated so that Farrow structure can be applied to realize the designed system. Also, the symmetric characteristics of filter coefficients are derived, which leads to the complexity reduction by saving almost a half of the number of coefficients. Moreover, all the elements of related vectors or matrices for the optimal process can be represented in closed forms, which make the design easier. Design example is also presented to illustrate the effectiveness of the proposed method.
Abstract: Fractional delay FIR filters design method based on
the differential evolution algorithm is presented. Differential evolution
is an evolutionary algorithm for solving a global optimization problems in the continuous search space. In the proposed approach,
an evolutionary algorithm is used to determine the coefficients of
a fractional delay FIR filter based on the Farrow structure. Basic
differential evolution is enhanced with a restricted mating technique,
which improves the algorithm performance in terms of convergence
speed and obtained solution. Evolutionary optimization is carried out by minimizing an objective function which is based on the amplitude
response and phase delay errors. Experimental results show that the proposed algorithm leads to a reduction in the amplitude response and phase delay errors relative to those achieved with the Least-Squares
method.
Abstract: Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.