Abstract: Fast speed drives for Permanent Magnet Synchronous
Motor (PMSM) is a crucial performance for the electric traction
systems. In this paper, PMSM is derived with a Model-based
Predictive Control (MPC) technique. Fast speed tracking is achieved
through optimization of the DC source utilization using MPC. The
technique is based on predicting the optimum voltage vector applied
to the driver. Control technique is investigated by comparing to the
cascaded PI control based on Space Vector Pulse Width Modulation
(SVPWM). MPC and SVPWM-based FOC are implemented with the
TMS320F2812 DSP and its power driver circuits. The designed MPC
for a PMSM drive is experimentally validated on a laboratory test
bench. The performances are compared with those obtained by a
conventional PI-based system in order to highlight the improvements,
especially regarding speed tracking response.
Abstract: In this paper, the effect of addition the dune sand powder (DSP) on development of compressive strength and hydration of cement pastes was investigated as a function of water/binder ratio, was varied, on the one hand, the percentage of DSP and on the other, the fineness of DSP. In order to understand better the pozzolanic effect of dune sand powder in cement pastes, we followed the mixtures hydration (50% Pure Lime + 50% DSP) by X-ray diffraction. These mixtures the pastes present a hydraulic setting which is due to the formation of a C-S-H phase (calcium silicate hydrate). The latter is semi-crystallized. This study is a simplified approach to that of the mixtures (80% ordinary Portland cement + 20% DSP), in which the main reaction is the fixing of the lime coming from the cement hydration in the presence of DSP, to form calcium silicate hydrate semi-crystallized of second generation. The results proved that up to (20% DSP) as Portland cement replacement could be used with a fineness of 4000 cm²/g without affecting adversely the compressive strength. After 28 days, the compressive strength at 5, 10 and 15% DSP is superior to Portland cement, with an optimum effect for a percentage of the order of 5% to 10% irrespective of the w/b ratio and fineness of DSP.
Abstract: Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.
Abstract: The presence of harmonic in power system is a major
concerned to power engineers for many years. With the increasing
usage of nonlinear loads in power systems, the harmonic pollution
becomes more serious. One of the widely used computation
algorithm for harmonic analysis is fast Fourier transform (FFT). In
this paper, a harmonic analyzer using FFT was implemented on
TMS320C6713 DSK. The supply voltage of 240 V 59 Hz is stepped
down to 5V using a voltage divider in order to match the power
rating of the DSK input. The output from the DSK was displayed on
oscilloscope and Code Composer Studio™ software. This work has
demonstrated the possibility of analyzing the 240V power supply
harmonic content using the DSK board.
Abstract: An efficient parallel form in digital signal processor can improve the algorithm performance. The butterfly structure is an important role in fast Fourier transform (FFT), because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which call as novel memory reference reduction methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. In this paper, we propose a parallel-computing approach for FFT implementation on digital signal processor (DSP) which is based on data-independent property and still hold the property of low-memory reference. The proposed method combines final two steps in NMRRM FFT to perform a novel data-independent structure, besides it is very suitable for multi-operation-unit digital signal processor and dual-core system. We have applied the proposed method of radix-2 FFT algorithm in low memory reference on TI TMSC320C64x DSP. Experimental results show the method can reduce 33.8% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property.