Abstract: Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.
Abstract: In this work, we use machine learning and data analysis techniques to predict the one-year mortality of cirrhotic patients. Data from 2,322 patients with liver cirrhosis are collected at a single medical center. Different machine learning models are applied to predict one-year mortality. A comprehensive feature space including demographic information, comorbidity, clinical procedure and laboratory tests is being analyzed. A temporal pattern mining technic called Frequent Subgraph Mining (FSM) is being used. Model for End-stage liver disease (MELD) prediction of mortality is used as a comparator. All of our models statistically significantly outperform the MELD-score model and show an average 10% improvement of the area under the curve (AUC). The FSM technic itself does not improve the model significantly, but FSM, together with a machine learning technique called an ensemble, further improves the model performance. With the abundance of data available in healthcare through electronic health records (EHR), existing predictive models can be refined to identify and treat patients at risk for higher mortality. However, due to the sparsity of the temporal information needed by FSM, the FSM model does not yield significant improvements. Our work applies modern machine learning algorithms and data analysis methods on predicting one-year mortality of cirrhotic patients and builds a model that predicts one-year mortality significantly more accurate than the MELD score. We have also tested the potential of FSM and provided a new perspective of the importance of clinical features.
Abstract: In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.
Abstract: In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.
Abstract: The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.
Abstract: In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm2.
Abstract: This paper presents Buck-Boost converter topology to maintain the input power factor by using the power factor stage control and regulation stage control. Suppose, if we are using the RL load the power factor will be reduced due to the presence of total harmonic distortion in the current wave. To improve the power factor the current waveform should follow the fundamental component of the voltage waveform. These can be achieved by using the high -frequency power converter. Based on the resonant circuit the converter is able to perform the function of Buck, Boost, and buck-boost converter. Here ,we have used Buck-Boost converter, because, the buck-boost converter has more advantages than the boost converter. Here the switching action of the power converter can take place by using the external zero comparator PFC stage control. The power converter consisting of the resonant circuit which is used to control the output voltage gain of the converter. The power converter is operated at a very high switching frequency in the range of 400KHz in order to overcome the switching losses of the power converter. Due to presence of high switching frequency, the power factor will improve. Therefore, the total harmonics distortion present in the current waveform has also reduced. These results has generated in the form of simulation by using MATLAB/SIMULINK software. Similar to the Buck and Boost converters, the operation of the Buck-Boost has best understood, in terms of the inductor's "reluctance" for allowing rapid change in current, which also reduces the Total Harmonic Distortion (THD) in the input current waveform, which can improve the input Power factor, based on the type of load used.
Abstract: With the advancement of knowledge about the utility
and impact of sustainability, its feasibility has been explored into
different walks of life. Scientists, however; have established their
knowledge in four areas viz environmental, economic, social and
cultural, popularly termed as four pillars of sustainability. Aspects of
environmental and economic sustainability have been rigorously
researched and practiced and huge volume of strong evidence of
effectiveness has been founded for these two sub-areas. For the social
and cultural aspects of sustainability, dependable evidence of
effectiveness is still to be instituted as the researchers and
practitioners are developing and experimenting methods across the
globe. Therefore, the present research aimed to identify globally used
practices of social and cultural sustainability and through evidence
synthesis assess their outcomes to determine the effectiveness of
those practices. A PICO format steered the methodology which
included all populations, popular sustainability practices including
walkability/cycle tracks, social/recreational spaces, privacy, health &
human services and barrier free built environment, comparators
included ‘Before’ and ‘After’, ‘With’ and ‘Without’, ‘More’ and
‘Less’ and outcomes included Social well-being, cultural coexistence,
quality of life, ethics and morality, social capital, sense of
place, education, health, recreation and leisure, and holistic
development. Search of literature included major electronic
databases, search websites, organizational resources, directory of
open access journals and subscribed journals. Grey literature,
however, was not included. Inclusion criteria filtered studies on the
basis of research designs such as total randomization, quasirandomization,
cluster randomization, observational or single studies
and certain types of analysis. Studies with combined outcomes were
considered but studies focusing only on environmental and/or
economic outcomes were rejected. Data extraction, critical appraisal
and evidence synthesis was carried out using customized tabulation,
reference manager and CASP tool. Partial meta-analysis was carried
out and calculation of pooled effects and forest plotting were done.
As many as 13 studies finally included for final synthesis explained
the impact of targeted practices on health, behavioural and social
dimensions. Objectivity in the measurement of health outcomes
facilitated quantitative synthesis of studies which highlighted the
impact of sustainability methods on physical activity, Body Mass
Index, perinatal outcomes and child health. Studies synthesized
qualitatively (and also quantitatively) showed outcomes such as
routines, family relations, citizenship, trust in relationships, social
inclusion, neighbourhood social capital, wellbeing, habitability and
family’s social processes. The synthesized evidence indicates slight
effectiveness and efficacy of social and cultural sustainability on the
targeted outcomes. Further synthesis revealed that such results of this
study are due weak research designs and disintegrated implementations. If architects and other practitioners deliver their
interventions in collaboration with research bodies and policy
makers, a stronger evidence-base in this area could be generated.
Abstract: Hemoglobin (HB) indicates anemia level and by
extension may reflect the nutritional level and perhaps the immunity
of an individual. Some antiretroviral drugs like Zidovudine are
known to cause anemia in people living with HIV/AIDS (PLWHA).
A cross sectional study using demographic data and blood specimen
from 218 female commercial sex workers attending antiretroviral
therapy (ART) clinics was conducted between December, 2009 and
July, 2011 to assess the effect of zidovudine on hematologic, and
RNA viral load of female sex workers receiving antiretroviral
treatment in north western Nigeria. Anemia is a common and serious
complication of both HIV infection and its treatment. In the setting of
HIV infection, anemia has been associated with decreased quality of
life, functional status, and survival. Antiretroviral therapy,
particularly the highly active antiretroviral therapy (HAART), has
been associated with a decrease in the incidence and severity of
anemia in HIV-infected patients who have received a HAART
regimen for at least 1 year. In this study, result has shown that of the
218 patients, 26 with hemoglobin count between 5.1 – 10g/dl were
observed to have the highest viral load count of 300,000 –
350,000copies/ml. It was also observed that most patients (190) with
HB of 10.1 – 15.0g/dl had viral load count of 200,000 – 250,000
copies /ml. An inverse relationship therefore exists i.e. the lower the
hemoglobin level, the higher the viral load count even though the test
statistics did not show any significance between the two (P = 0.206).
This shows that multivariate logistic regression analysis
demonstrated that anemia was associated with a CD4 + cell count
below 50/μL, female sex workers with a viral load above 100,000
copies/mL, who use zidovudine.
Severe anemia was less prevalent in this study population than in
historical comparators; however, mild to moderate anemia rates
remain high. The study therefore recommends that hematological and
virologic parameters be monitored closely in patients receiving first
line ART regimen.
Abstract: This paper presents the development of a single-ended 38.5 kS/s 10-bit programmable reference SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and a SAR digital logic to create 10 effective bits ADC. A programmable reference circuitry allows the ADC to operate with different input range from 0.6 V to 2.1 V. The ADC consumed less than 7.5 mW power with a 3 V supply.
Abstract: Securing the confidential data transferred via wireless
network remains a challenging problem. It is paramount to ensure
that data are accessible only by the legitimate users rather than by the
attackers. One of the most serious threats to organization is jamming,
which disrupts the communication between any two pairs of nodes.
Therefore, designing an attack-defending scheme without any packet
loss in data transmission is an important challenge. In this paper,
Dependence based Malicious Route Defending DMRD Scheme has
been proposed in multi path routing environment to prevent jamming
attack. The key idea is to defend the malicious route to ensure
perspicuous transmission. This scheme develops a two layered
architecture and it operates in two different steps. In the first step,
possible routes are captured and their agent dependence values are
marked using triple agents. In the second step, the dependence values
are compared by performing comparator filtering to detect malicious
route as well as to identify a reliable route for secured data
transmission. By simulation studies, it is observed that the proposed
scheme significantly identifies malicious route by attaining lower
delay time and route discovery time; it also achieves higher
throughput.
Abstract: The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.
Abstract: This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.
Abstract: At receiving high data rate in ultra wideband (UWB) technology for many users, there are multiple user interference and inter-symbol interference as obstacles in the multi-path reception technique. Since the rake receivers were designed to collect many resolvable paths, even more than hundred of paths. Rake receiver implementation structures have been proposed towards increasing the complexity for getting better performances in indoor or outdoor multi-path receivers by reducing the bit error rate (BER). So several rake structures were proposed in the past to reduce the number of combining and estimating of resolvable paths. To this aim, we suggested two improved rake receivers based on signal sign separation in the maximal ratio combiner (MRC), called positive-negative MRC selective rake (P-N/MRC-S-rake) and positive-negative MRC partial rake (P-N/MRC-S-rake) receivers. These receivers were introduced to reduce the complexity with less number of fingers and improving the performance with low BER. Before decision circuit, there is a comparator to compare between positive quantity and negative quantity to decide whether the transmitted bit is 1 or 0. The BER was driven by MATLAB simulation with multi-path environments for impulse radio time-hopping binary phase shift keying (TH-BPSK) modulation and the results were compared with those of conventional rake receivers.
Abstract: This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.
Abstract: This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.
Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigma-delta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigma-delta modulator improves the timing
margin about 16%. The sub-circuits of sigma-delta modulator such as
SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and
DWA are designed with the non-ideal characteristics taken into
account. The sigma-delta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.
Abstract: Direct Torque Control is a control technique in AC
drive systems to obtain high performance torque control. The
conventional DTC drive contains a pair of hysteresis comparators.
DTC drives utilizing hysteresis comparators suffer from high torque
ripple and variable switching frequency. The most common solution
to those problems is to use the space vector depends on the reference
torque and flux. In this Paper The space vector modulation technique
(SVPWM) is applied to 2 level inverter control in the proposed
DTC-based induction motor drive system, thereby dramatically
reducing the torque ripple. Then the controller based on space vector
modulation is designed to be applied in the control of Induction
Motor (IM) with a three-level Inverter. This type of Inverter has
several advantages over the standard two-level VSI, such as a greater
number of levels in the output voltage waveforms, Lower dV/dt, less
harmonic distortion in voltage and current waveforms and lower
switching frequencies. This paper proposes a general SVPWM
algorithm for three-level based on standard two-level SVPWM. The
proposed scheme is described clearly and simulation results are
reported to demonstrate its effectiveness. The entire control scheme is
implemented with Matlab/Simulink.
Abstract: A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.