An Address-Oriented Transmit Mechanism for GALS NoC

Since Network-on-Chip (NoC) uses network interfaces (NIs) to improve the design productivity, by now, there have been a few papers addressing the design and implementation of a NI module. However, none of them considered the difference of address encoding methods between NoC and the traditional bus-shared architecture. On the basis of this difference, in the paper, we introduce a transmit mechanism to solve such a problem for global asynchronous locally synchronous (GALS) NoC. Furthermore, we give the concrete implementation of the NI module in this transmit mechanism. Finally, we evaluate its performance and area overhead by a VHDL-based cycle-accurate RTL model and simulation results confirm the validity of this address-oriented transmit mechanism.

Mitigation of Radiation Levels for Base Transceiver Stations based on ITU-T Recommendation K.70

This essay presents applicative methods to reduce human exposure levels in the area around base transceiver stations in a environment with multiple sources based on ITU-T recommendation K.70. An example is presented to understand the mitigation techniques and their results and also to learn how they can be applied, especially in developing countries where there is not much research on non-ionizing radiations.

A Novel Spectrum Sensing Scheme Based on Periodicity of DVB-T Pilot Signals

This paper proposes a novel spectrum sensing technique for the digital video broadcasting-terrestrial (DVB-T) systems, which utilizes the periodicity of pilot signals in the orthogonal frequency division multiplexing (OFDM) symbols. The proposed scheme can overcome the effect of the timing synchronization error by recorrelating the correlation values in the same sample distances. The numerical results demonstrate that the detection probability performance of the proposed scheme outperforms that of the conventional scheme when there exists a timing synchronization error.

Blind Source Separation based on the Estimation for the Number of the Blind Sources under a Dynamic Acoustic Environment

Independent component analysis can estimate unknown source signals from their mixtures under the assumption that the source signals are statistically independent. However, in a real environment, the separation performance is often deteriorated because the number of the source signals is different from that of the sensors. In this paper, we propose an estimation method for the number of the sources based on the joint distribution of the observed signals under two-sensor configuration. From several simulation results, it is found that the number of the sources is coincident to that of peaks in the histogram of the distribution. The proposed method can estimate the number of the sources even if it is larger than that of the observed signals. The proposed methods have been verified by several experiments.

Fault Zone Detection on Advanced Series Compensated Transmission Line using Discrete Wavelet Transform and SVM

In this paper a novel method for finding the fault zone on a Thyristor Controlled Series Capacitor (TCSC) incorporated transmission line is presented. The method makes use of the Support Vector Machine (SVM), used in the classification mode to distinguish between the zones, before or after the TCSC. The use of Discrete Wavelet Transform is made to prepare the features which would be given as the input to the SVM. This method was tested on a 400 kV, 50 Hz, 300 Km transmission line and the results were highly accurate.

The Effect of a Graded Band Gap Window on the Performance of a Single Junction AlxGa1-xAs/GaAs Solar Cell

We have modeled the effect of a graded band gap window on the performance of a single junction AlxGa1-xAs/GaAs solar cell. First, we study the electrical characteristics of a single junction AlxGa1-xAs/GaAs solar cell, by employing an optimized structure for this solar cell, we show that grading the band gap of the window can increase the conversion efficiency of the solar cell by about 1.5%, and can also improve the quantum efficiency of the solar cell especially at shorter wavelengths.

Measurement of UHF Signal Strength Propagating from Road Surface with Vehicle Obstruction

Radio wave propagation on the road surface is a major problem on wireless sensor network for traffic monitoring. In this paper, we compare receiving signal strength on two scenarios 1) an empty road and 2) a road with a vehicle. We investigate the effect of antenna polarization and antenna height to the receiving signal strength. The transmitting antenna is installed on the road surface. The receiving signal is measured 360 degrees around the transmitting antenna with the radius of 2.5 meters. Measurement results show the receiving signal fluctuation around the transmitting antenna in both scenarios. Receiving signal with vertical polarization antenna results in higher signal strength than horizontal polarization antenna. The optimum antenna elevation is 1 meter for both horizon and vertical polarizations with the vehicle on the road. In the empty road, the receiving signal level is unvarying with the elevation when the elevation is greater than 1.5 meters.

SFCL Location Selection Considering Reliability Indices

The fault current levels through the electric devices have a significant impact on failure probability. New fault current results in exceeding the rated capacity of circuit breaker and switching equipments and changes operation characteristic of overcurrent relay. In order to solve these problems, SFCL (Superconducting Fault Current Limiter) has rising as one of new alternatives so as to improve these problems. A fault current reduction differs depending on installed location. Therefore, a location of SFCL is very important. Also, SFCL decreases the fault current, and it prevents surrounding protective devices to be exposed to fault current, it then will bring a change of reliability. In this paper, we propose method which determines the optimal location when SFCL is installed in power system. In addition, the reliability about the power system which SFCL was installed is evaluated. The efficiency and effectiveness of this method are also shown by numerical examples and the reliability indices are evaluated in this study at each load points. These results show a reliability change of a system when SFCL was installed.

Modeling and Visualizing Seismic Wave Propagation in Elastic Medium Using Multi-Dimension Wave Digital Filtering Approach

A novel PDE solver using the multidimensional wave digital filtering (MDWDF) technique to achieve the solution of a 2D seismic wave system is presented. In essence, the continuous physical system served by a linear Kirchhoff circuit is transformed to an equivalent discrete dynamic system implemented by a MD wave digital filtering (MDWDF) circuit. This amounts to numerically approximating the differential equations used to describe elements of a MD passive electronic circuit by a grid-based difference equations implemented by the so-called state quantities within the passive MDWDF circuit. So the digital model can track the wave field on a dense 3D grid of points. Details about how to transform the continuous system into a desired discrete passive system are addressed. In addition, initial and boundary conditions are properly embedded into the MDWDF circuit in terms of state quantities. Graphic results have clearly demonstrated some physical effects of seismic wave (P-wave and S–wave) propagation including radiation, reflection, and refraction from and across the hard boundaries. Comparison between the MDWDF technique and the finite difference time domain (FDTD) approach is also made in terms of the computational efficiency.

Dual-Link Hierarchical Cluster-Based Interconnect Architecture for 3D Network on Chip

Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Performance Analysis of Wireless Ad-Hoc Network Based on EDCA IEEE802.11e

IEEE 802.11e is the enhanced version of the IEEE 802.11 MAC dedicated to provide Quality of Service of wireless network. It supports QoS by the service differentiation and prioritization mechanism. Data traffic receives different priority based on QoS requirements. Fundamentally, applications are divided into four Access Categories (AC). Each AC has its own buffer queue and behaves as an independent backoff entity. Every frame with a specific priority of data traffic is assigned to one of these access categories. IEEE 802.11e EDCA (Enhanced Distributed Channel Access) is designed to enhance the IEEE 802.11 DCF (Distributed Coordination Function) mechanisms by providing a distributed access method that can support service differentiation among different classes of traffic. Performance of IEEE 802.11e MAC layer with different ACs is evaluated to understand the actual benefits deriving from the MAC enhancements.

The Analysis of Photoconductive Semiconductor Switch Operation in the Frequency of 10 GHz

A device analysis of the photoconductive semiconductor switch is carried out to investigate distribution of electric field and carrier concentrations as well as the current density distribution. The operation of this device was then investigated as a switch operating in X band. It is shown that despite the presence of symmetry geometry, switch current density of the on-state steady state mode is distributed asymmetrically throughout the device.

C-V Characterization and Analysis of Temperature and Channel Thickness Effects on Threshold Voltage of Ultra-thin SOI MOSFET by Self-Consistent Model

The threshold voltage and capacitance voltage characteristics of ultra-thin Silicon-on-Insulator MOSFET are greatly influenced by the thickness and doping concentration of the silicon film. In this work, the capacitance voltage characteristics and threshold voltage of the device have been analyzed with quantum mechanical effects using the Self-Consistent model. Reduction of channel thickness and adding doping impurities cause an increase in the threshold voltage. Moreover, the temperature effects cause a significant amount of threshold voltage shift. The temperature dependence of threshold voltage has also been observed with Self- Consistent approach which are well supported from experimental performance of practical devices.

Analysis of a Novel Strained Silicon RF LDMOS

In this paper we propose a novel RF LDMOS structure which employs a thin strained silicon layer at the top of the channel and the N-Drift region. The strain is induced by a relaxed Si0.8 Ge0.2 layer which is on top of a compositionally graded SiGe buffer. We explain the underlying physics of the device and compare the proposed device with a conventional LDMOS in terms of energy band diagram and carrier concentration. Numerical simulations of the proposed strained silicon laterally diffused MOS using a 2 dimensional device simulator indicate improvements in saturation and linear transconductance, current drivability, cut off frequency and on resistance. These improvements are however accompanied with a suppression in the break down voltage.

The Impact of Process Parameters on the Output Characteristics of an LDMOS Device

In this paper, we have examined the effect of process parameter variation on the electrical characteristics of an LDMOS device. The rate of change in the electrical parameters such as cut off frequency, breakdown voltage and drain saturation current as a function of the process parameters is investigated

A New Hardware Implementation of Manchester Line Decoder

In this paper, we present a simple circuit for Manchester decoding and without using any complicated or programmable devices. This circuit can decode 90kbps of transmitted encoded data; however, greater than this transmission rate can be decoded if high speed devices were used. We also present a new method for extracting the embedded clock from Manchester data in order to use it for serial-to-parallel conversion. All of our experimental measurements have been done using simulation.

Improvement of Short Channel Effects in Cylindrical Strained Silicon Nanowire Transistor

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Distributed Generator Placement for Loss Reduction and Improvement in Reliability

Distributed Power generation has gained a lot of attention in recent times due to constraints associated with conventional power generation and new advancements in DG technologies .The need to operate the power system economically and with optimum levels of reliability has further led to an increase in interest in Distributed Generation. However it is important to place Distributed Generator on an optimum location so that the purpose of loss minimization and voltage regulation is dully served on the feeder. This paper investigates the impact of DG units installation on electric losses, reliability and voltage profile of distribution networks. In this paper, our aim would be to find optimal distributed generation allocation for loss reduction subjected to constraint of voltage regulation in distribution network. The system is further analyzed for increased levels of Reliability. Distributed Generator offers the additional advantage of increase in reliability levels as suggested by the improvements in various reliability indices such as SAIDI, CAIDI and AENS. Comparative studies are performed and related results are addressed. An analytical technique is used in order to find the optimal location of Distributed Generator. The suggested technique is programmed under MATLAB software. The results clearly indicate that DG can reduce the electrical line loss while simultaneously improving the reliability of the system.

Investigation of Inter Feeder Power Flow Regulator: Load Sharing Mode

The Inter feeder Power Flow Regulator (IFPFR) proposed in this paper consists of several voltage source inverters with common dc bus; each inverter is connected in series with one of different independent distribution feeders in the power system. This paper is concerned with how to transfer power between the feeders for load sharing purpose. The power controller of each inverter injects the power (for sending feeder) or absorbs the power (for receiving feeder) via injecting suitable voltage; this voltage injection is simulated by voltage drop across series virtual impedance, the impedance value is selected to achieve the concept of power exchange between the feeders without perturbing the load voltage magnitude of each feeder. In this paper a new control scheme for load sharing using IFPFR is proposed.

A Comparison Study of Electrical Characteristics in Conventional Multiple-gate Silicon Nanowire Transistors

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, triple gate, and gate all around nano wires were studied to investigate the impact of increasing the number of gates on the control of the short channel effect which is important in nanoscale devices. Also in the case of triple gate rectangular SNWT inserting extra gates on the bottom of device can improve the application of device. The results indicate that by using gate all around structures short channel effects such as DIBL, subthreshold swing and delay reduces.