Test Data Compression Using a Hybrid of Bitmask Dictionary and 2n Pattern Runlength Coding Methods
In VLSI, testing plays an important role. Major
problem in testing are test data volume and test power. The important
solution to reduce test data volume and test time is test data
compression. The Proposed technique combines the bit maskdictionary
and 2n pattern run length-coding method and provides a
substantial improvement in the compression efficiency without
introducing any additional decompression penalty. This method has
been implemented using Mat lab and HDL Language to reduce test
data volume and memory requirements. This method is applied on
various benchmark test sets and compared the results with other
existing methods. The proposed technique can achieve a compression
ratio up to 86%.
[1] Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, “VLSI Test
Principles and Architectures: Design for Testability”, Morgan
Kaufmann; Academic Press; Newnes (781)- 2006-313-4732.
[2] N.A. Touba, "Survey of Test Vector Compression Techniques", IEEE
Design & Test Magazine, Vol. 23, Issue 4, Jul. 2006, pp-294-303.
[3] Kalamani. C and Dr. K. Paramasivam, “Survey of Low Power Testing
Using Compression Techniques'', International Journal of Electronics &
Communication Technology , Vol.4, Issue 4, Oct-Dec 2013,pp. 13-18.
[4] V. Iyengar, K. Chakrabarty, and B. T. Murray, “Huffman encoding of
test sets for sequential circuits'', IEEE Transactions on Instrumentation
and Measurement, vol. 47, February 1998, pp. 21-25.
[5] A. Jas, and N. A. Touba, et al, “An efficient Test vector compression
scheme using selective Huffman coding”,IEEE Trans Comput-Aided
Des Integr, Circuits Syst.,vol.22,no.6,jun.2003, pp.797-806.
[6] X. Kavousianos, E. Kalligeros and D. Nikolos, “Optical selective
Huffman Coding for test data compression”, IEEE Trans comput, vol.56,
no.8, Aug.2007, pp.1146-1152.
[7] Gonciari. P. T., “Variable length input Huffman coding for system-on-achip
test”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.
22, no.6, Jun.2003, pp. 783–796.
[8] Chandra and K. Chakrabarty, “System-on-a-chip data compression and
decompression architecture based on Golomb codes,” IEEE Trans.
Comput.-Aided Des. Integr. Circuits Syst., vol. 20, no. 3, Mar. 2001, pp.
355–368.
[9] A. Chandra and K. Chakrabarty, “Test Data Compression and Test
Resource Partitioning for system on chip using Frequency Directed Run
length coding”, IEEE Trans. Comput., vol.52,no8, Mar 2003, pp. 352-
363.
[10] Aiman El-Maleh et al, “Test Data Compression for System-on-a-Chip
using Extended Frequency-Directed Run-Length (EFDR) Code,” IET
Computers & Digital Techniques, vol. 2, No. 3, 2008, pp. 155–163.
[11] M. Nourani and M. Tehranipour, “RL-Huffman encoding for test
compression and power reduction in scan application”, ACM Trans.Des.
Automat Electron Syst., vol.10, no.1, 2005, pp. 91-115.
[12] Lung-Jen Lee, Wang-Dauh Tseng, and Rung-Bin Lin, “An Internal
Pattern Run-Length Methodology for Slice Encoding”, ETRI Journal,
Volume 33, Number 3, June 2011.
[13] H. Hashempour, L. Schiano, and F. Lombardi, “Error-resilient test data
compression using Tunstall codes”, in Proc. IEEE Int. Symp.
DefectFault Tolerance VLSI Syst., 2004, pp. 316–323.
[14] M. Knieser, F. Wolff, C. Papachristou, D. Weyer, and D. McIntyre, “A
technique for high ratio LZW compression”, in Proc. Des., Autom., Test
Eur., 2003, pp. 10116.
[15] M. Tehranipour, M. Nourani, and K. Chakrabarty, “Nine-coded compression
technique for testing embedded cores in SOCs”, IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 13, Jun. 2005, pp. 719–731.
[16] L. Lingappan, S. Ravi, et al, “Test-volume reduction in systems-on-achip
using heterogeneous and multilevel compression techniques”, IEEE
Trans.Comput.-Aided Des Integr. Circuits Syst., vol. 25, no. 10, Oct.
2006, pp.2193–2206.
[17] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel Huffman
coding: An efficient test-data compression method for IP cores”, IEEE
Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 6, Jun.
2007 pp.1070–1083.
[18] Seok-Won Seong and Prabhat Mishra, “Bitmask-Based Code
Compression for Embedded Systems”, IEEE Transactions on computeraided
design of integrated circuits and systems, 2008.
[19] Kanad Basu, Prabhat Mishra, “Test Data Compression Using Efficient
Bitmask and Dictionary Selection”, IEEE Transactions on Very Large
Scale Integration (VLSI) systems, vol. 18, no. 9, September 2010.
[20] Lung-Jen Lee, et al, “2n Pattern Run-Length for Test Data
Compression”, IEEE transactions on computer- aided design of
integrated circuits and systems, vol. 31, no. 4, April 2012.
[21] Wang-Dauh Tseng & Lung-Jen Lee, “A Multidimensional Pattern Run
Length method for test data compression”, in proc. Asian Test Symp,
2009, pp. 111-116.
[1] Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, “VLSI Test
Principles and Architectures: Design for Testability”, Morgan
Kaufmann; Academic Press; Newnes (781)- 2006-313-4732.
[2] N.A. Touba, "Survey of Test Vector Compression Techniques", IEEE
Design & Test Magazine, Vol. 23, Issue 4, Jul. 2006, pp-294-303.
[3] Kalamani. C and Dr. K. Paramasivam, “Survey of Low Power Testing
Using Compression Techniques'', International Journal of Electronics &
Communication Technology , Vol.4, Issue 4, Oct-Dec 2013,pp. 13-18.
[4] V. Iyengar, K. Chakrabarty, and B. T. Murray, “Huffman encoding of
test sets for sequential circuits'', IEEE Transactions on Instrumentation
and Measurement, vol. 47, February 1998, pp. 21-25.
[5] A. Jas, and N. A. Touba, et al, “An efficient Test vector compression
scheme using selective Huffman coding”,IEEE Trans Comput-Aided
Des Integr, Circuits Syst.,vol.22,no.6,jun.2003, pp.797-806.
[6] X. Kavousianos, E. Kalligeros and D. Nikolos, “Optical selective
Huffman Coding for test data compression”, IEEE Trans comput, vol.56,
no.8, Aug.2007, pp.1146-1152.
[7] Gonciari. P. T., “Variable length input Huffman coding for system-on-achip
test”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.
22, no.6, Jun.2003, pp. 783–796.
[8] Chandra and K. Chakrabarty, “System-on-a-chip data compression and
decompression architecture based on Golomb codes,” IEEE Trans.
Comput.-Aided Des. Integr. Circuits Syst., vol. 20, no. 3, Mar. 2001, pp.
355–368.
[9] A. Chandra and K. Chakrabarty, “Test Data Compression and Test
Resource Partitioning for system on chip using Frequency Directed Run
length coding”, IEEE Trans. Comput., vol.52,no8, Mar 2003, pp. 352-
363.
[10] Aiman El-Maleh et al, “Test Data Compression for System-on-a-Chip
using Extended Frequency-Directed Run-Length (EFDR) Code,” IET
Computers & Digital Techniques, vol. 2, No. 3, 2008, pp. 155–163.
[11] M. Nourani and M. Tehranipour, “RL-Huffman encoding for test
compression and power reduction in scan application”, ACM Trans.Des.
Automat Electron Syst., vol.10, no.1, 2005, pp. 91-115.
[12] Lung-Jen Lee, Wang-Dauh Tseng, and Rung-Bin Lin, “An Internal
Pattern Run-Length Methodology for Slice Encoding”, ETRI Journal,
Volume 33, Number 3, June 2011.
[13] H. Hashempour, L. Schiano, and F. Lombardi, “Error-resilient test data
compression using Tunstall codes”, in Proc. IEEE Int. Symp.
DefectFault Tolerance VLSI Syst., 2004, pp. 316–323.
[14] M. Knieser, F. Wolff, C. Papachristou, D. Weyer, and D. McIntyre, “A
technique for high ratio LZW compression”, in Proc. Des., Autom., Test
Eur., 2003, pp. 10116.
[15] M. Tehranipour, M. Nourani, and K. Chakrabarty, “Nine-coded compression
technique for testing embedded cores in SOCs”, IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 13, Jun. 2005, pp. 719–731.
[16] L. Lingappan, S. Ravi, et al, “Test-volume reduction in systems-on-achip
using heterogeneous and multilevel compression techniques”, IEEE
Trans.Comput.-Aided Des Integr. Circuits Syst., vol. 25, no. 10, Oct.
2006, pp.2193–2206.
[17] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel Huffman
coding: An efficient test-data compression method for IP cores”, IEEE
Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 6, Jun.
2007 pp.1070–1083.
[18] Seok-Won Seong and Prabhat Mishra, “Bitmask-Based Code
Compression for Embedded Systems”, IEEE Transactions on computeraided
design of integrated circuits and systems, 2008.
[19] Kanad Basu, Prabhat Mishra, “Test Data Compression Using Efficient
Bitmask and Dictionary Selection”, IEEE Transactions on Very Large
Scale Integration (VLSI) systems, vol. 18, no. 9, September 2010.
[20] Lung-Jen Lee, et al, “2n Pattern Run-Length for Test Data
Compression”, IEEE transactions on computer- aided design of
integrated circuits and systems, vol. 31, no. 4, April 2012.
[21] Wang-Dauh Tseng & Lung-Jen Lee, “A Multidimensional Pattern Run
Length method for test data compression”, in proc. Asian Test Symp,
2009, pp. 111-116.
@article{"International Journal of Information, Control and Computer Sciences:70940", author = "C. Kalamani and K. Paramasivam", title = "Test Data Compression Using a Hybrid of Bitmask Dictionary and 2n Pattern Runlength Coding Methods", abstract = "In VLSI, testing plays an important role. Major
problem in testing are test data volume and test power. The important
solution to reduce test data volume and test time is test data
compression. The Proposed technique combines the bit maskdictionary
and 2n pattern run length-coding method and provides a
substantial improvement in the compression efficiency without
introducing any additional decompression penalty. This method has
been implemented using Mat lab and HDL Language to reduce test
data volume and memory requirements. This method is applied on
various benchmark test sets and compared the results with other
existing methods. The proposed technique can achieve a compression
ratio up to 86%.", keywords = "Bit Mask dictionary, 2n pattern run length code,
system-on-chip, SOC, test data compression.", volume = "9", number = "3", pages = "831-6", }
