A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 processor, and average 6.5% power saving is observed when DVFS is applied under the deadline condition.

• Hwan Su Jung
• Ahn Jun Gil
• Jong Tae Kim

• Deadline
• Dynamic Voltage Frequency Scaling
• Power State Transition.

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