Asynchronous Microcontroller Simulation Model in VHDL
This article describes design of the 8-bit asynchronous
microcontroller simulation model in VHDL. The model is created in
ISE Foundation design tool and simulated in Modelsim tool. This
model is a simple application example of asynchronous systems
designed in synchronous design tools. The design process of creating
asynchronous system with 4-phase bundled-data protocol and with
matching delays is described in the article. The model is described in
gate-level abstraction.
The simulation waveform of the functional construction is the
result of this article. Described construction covers only the
simulation model. The next step would be creating synthesizable
model to FPGA.
[1] Sparso, J. Furber, S. Principles of Asynchronous Circuit Design - A
System Perspective. Boston: Kluwer Academic Publishers, 2001.
[2] Hauck, S. Asynchronous Design Methodologies: An Overview. In
Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995.
[3] Hwang, O. E. Digital Logic and Microprocessor Design with VHDL.
Riverside: La Sierra University, 2004. ISBN: 0-534-46593-5.
[4] Perry, L. D. VHDL: Programming by Example: Fourth Edition.
McGraw-Hill, 2002.
[1] Sparso, J. Furber, S. Principles of Asynchronous Circuit Design - A
System Perspective. Boston: Kluwer Academic Publishers, 2001.
[2] Hauck, S. Asynchronous Design Methodologies: An Overview. In
Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995.
[3] Hwang, O. E. Digital Logic and Microprocessor Design with VHDL.
Riverside: La Sierra University, 2004. ISBN: 0-534-46593-5.
[4] Perry, L. D. VHDL: Programming by Example: Fourth Edition.
McGraw-Hill, 2002.
@article{"International Journal of Electrical, Electronic and Communication Sciences:50715", author = "M. Kovac", title = "Asynchronous Microcontroller Simulation Model in VHDL", abstract = "This article describes design of the 8-bit asynchronous
microcontroller simulation model in VHDL. The model is created in
ISE Foundation design tool and simulated in Modelsim tool. This
model is a simple application example of asynchronous systems
designed in synchronous design tools. The design process of creating
asynchronous system with 4-phase bundled-data protocol and with
matching delays is described in the article. The model is described in
gate-level abstraction.
The simulation waveform of the functional construction is the
result of this article. Described construction covers only the
simulation model. The next step would be creating synthesizable
model to FPGA.", keywords = "Asynchronous, Microcontroller, VHDL, FPGA.", volume = "2", number = "9", pages = "1763-4", }